Integrated circuits find application in many of today's consumer electronics, such as cell phones, video cameras, portable music players, printers, computers, etc. Integrated circuits may include a combination of active devices, passive devices and their interconnections.
Integrated circuit fabrication typically requires a multitude of photomasks, wherein each photomask defines a specific design level that serves a particular purpose. The photomask may contain a series of shapes indicating the regions that are to be processed by the particular manufacturing step that uses the photomask. The combination of all of the shapes in the photomask set, when processed in order, forms the circuitry of the integrated circuit product.
Generally, an integrated circuit layout consists of two categories of data: design layers (designed by a layout designer) and non-design layers (layers generated with Boolean algorithms and typically done by a foundry). These design and non-design layers can be formed by Boolean algorithms ranging from the simple to the complicated, which can require special sizing.
Unfortunately, complicated Boolean algorithms can produce singularities and sub-geometry features, such as slit and slot features, within the mask level data. The singularities and sub-geometries represent unintentional features that have a size that is below the minimum feature size of the integrated circuit technology. An example of this may be an inadvertent joining of two rectangles, in a 90 nm technology, that has a cross-section of less than 2 nm. The resolution of the 90 nm technology might not be able to reliably support the cross-section size which can lead to manufacturing problems, lower wafer yields, and increased costs.
Some of these sub-geometries can be removed at the layout data level by the application of a size up/size down cleaning rule, wherein some of the polygons are sized up to remove the sub-geometry feature formed between them, and then re-sized down to obtain a resultant dimension that does not impact device performance. If the sub-geometries are not addressed unexpected or parasitic devices could be formed that can damage an operating electronic device.
However, a simple sizing rule does not work for all structures and some sub-geometries and singularities may remain. As a result, a mask writing tool may not be able to resolve the pattern and/or the sub-geometries left behind and the mask inspection tool will find the mask difficult to inspect. Additionally, a lithographer might see sub-geometries printed on the wafer, which can increase the likelihood or chance of resist lifting that can adversely affect wafer yield and device performance.
Thus, a need still remains for an integrated circuit system with sub-geometry removal. In view of the continuing trend to increase the electronic content in personal devices, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.